1. Field of the Invention
The present invention relates to the virtual address translation in a central processing unit (CPU).
2. Description of Background
A translation lookaside buffer (TLB) is a cache in a CPU that is used to improve the speed of virtual address translations. It references the most recently used page table entries and translates linear addresses into physical addresses directly without having to access page tables and other translation tables from main memory.
In many server computer systems a CPU is dynamically assigned to different tasks or even virtualization levels (e.g., host, guest environment), with the result that the TLB of the CPU has to buffer entries of different attributes, i.e. for different tasks etc. An example for such computer environment is described in the U.S. Pat. No. 5,317,705. For various reasons the operating system executed by a CPU has to purge all associated TLB entries of the task, this CPU is currently assigned to; e.g. when a translation table in main memory is modified. In this case it is desirable to keep TLB entries of other tasks, but purge only those entries, randomly distributed in the TLB, associated to the current task.
A common method used to implement this purging process is to use a content-addressable memory (CAM) implementation for the TLB, which is usually composed of static random access memory (SRAM) with added comparison circuitry for each location in a random access memory (RAM) that enable a search operation to complete in a single clock cycle. This extra circuitry increases manufacturing cost and also increases power dissipation since every comparison circuit is active on every clock cycle.
In less costly implementations only RAM circuitries are used and the hardware scans through all RAM locations, compares each data word outside the RAM, and purges the data word in RAM in case of a match. This “TLB table walking” method is extremely time-consuming since every TLB RAM location must be read-out, compared and written back in case of a match.